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. U Non-Transparent 21555 t4 Bridge ee h
Product Features
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PCI-to-PCI
Datasheet
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Full compliance with the PCI local Bus Specification, Revision 2.2, plus: -- PCI Power Management support -- Vital Product Data (VPD) support -- CompactPCI Distributed Hot-Swap support 3.3-V operation with 5.0-V tolerant I/O Selectable asynchronous or synchronous primary and secondary interface clocks Concurrent primary and secondary bus operation Fully compliant with the Advanced Configuration Power Interface (ACPI) specification Fully compliant with the PCI Bus Power Management specification Queuing of multiple transactions in either direction 256 bytes of posted write (data and address) buffering in each direction 256 bytes of read data buffering in each direction Four delayed transaction entries in each direction Two dedicated I2O delayed transaction entries Two sets of standard PCI Configuration registers corresponding to the primary and secondary interface; each set is accessible from either the primary or secondary interface Direct offset address translation for downstream memory and I/O transactions Hardware enable for secondary bus central functions IEEE Standard 1149.1 boundary-scan JTAG interface
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Four primary interface base address configuration registers for downstream forwarding, with size and prefetchability programmable for all four address ranges Three secondary interface address configuration registers specifying local address ranges for upstream forwarding, with size and prefetchability programmable for all three address ranges Inverse decoding above the 4 GB address boundary for upstream DACs Ability to generate Type 0 and Type 1 configuration commands on the primary or secondary interface via configuration or I/O CSR accesses Ability to generate I/O commands on the primary or secondary interface via I/O CSR accesses I2O message unit Doorbell registers for software generation of primary and secondary bus interrupts, 16 bits per interface Eight Dwords of scratchpad registers Generic own bit (can memory-map) semaphore Parallel flash ROM interface with primary bus expansion ROM base address register Serial ROM interface Secondary bus arbiter support for up to nine external devices at 33 MHz and up to four external devices at 66 MHz (in addition to the 21555) Secondary bus clock output for synchronous operation Four 32-bit base address configuration registers mapping the 21555 control and status registers (CSRs) Available in 33 MHz and 66 MHz versions
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Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
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Order Number: 278320-002
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 21555 Non-Transparent PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
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Datasheet
Contents
Contents
1.0 Introduction.................................................................................................................................... 5 1.1 1.2 2.0 2.1 2.2 3.0 3.1 3.2 3.3 3.4 Comparing 21555 and Standard PCI-to-PCI Bridge ............................................................. 5 Architectural Overview.......................................................................................................... 8 Pin Location List (Alphanumeric) ........................................................................................12 Pin Signal List (Alphanumeric)............................................................................................17 PCI Electrical Specification Conformance ..........................................................................22 Absolute Maximum Ratings ................................................................................................22 DC Specifications ...............................................................................................................23 AC Timing Specifications .................................................................................................... 23 3.4.1 Clock Timing Specifications ...................................................................................23 3.4.2 PCI Signal Timing Specifications ...........................................................................25 3.4.3 Reset Timing Specifications ..................................................................................26 3.4.4 Serial ROM Timing Specifications .........................................................................27 3.4.5 Parallel ROM Timing Specifications.......................................................................27 3.4.6 JTAG Timing Specifications...................................................................................28
Pin Assignment ...........................................................................................................................10
Electrical Specifications .............................................................................................................22
4.0
Mechanical Specifications ..........................................................................................................29
Figures
1 2 3 4 5 6 21555 Intelligent Controller Application ........................................................................................ 6 21555 Microarchitecture ............................................................................................................... 9 21555 PBGA Cavity Down View.................................................................................................11 PCI Clock Signal AC Parameter Measurements ........................................................................25 PCI Signal Timing Measurement Conditions ..............................................................................25 304 PBGA (Four-Layer) Package...............................................................................................29
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21555 and PPB Feature Comparison...........................................................................................7 Signal Type Abbreviations ..........................................................................................................10 21555 Pin Location List (Alphanumeric) .....................................................................................12 21555 Pin Signal List (Alphanumeric).........................................................................................17 Absolute Maximum Ratings ........................................................................................................22 Functional Operating Range.......................................................................................................22 DC Parameters ...........................................................................................................................23 33 MHz PCI Clock Signal AC Parameters..................................................................................24 66 MHz PCI Clock Signal AC Parameters..................................................................................24 33 MHz PCI Signal Timing Specifications ..................................................................................26 66 MHz PCI Signal Timing Specifications ..................................................................................26 Reset Timing Specifications .......................................................................................................26 Serial ROM Timing Specifications ..............................................................................................27 Parallel ROM Timing Specifications ...........................................................................................27 JTAG Timing Specifications........................................................................................................28
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16 304-Point 4-Layer PBGA Package Dimensions ......................................................................... 30
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Non-Transparent PPB
1.0
Introduction
Intel's 21555 is a PCI peripheral device that performs PCI bridging functions for embedded and intelligent I/O applications. The 21555 has a 64-bit primary interface, a 64-bit secondary interface, and 66-MHz capability. The 21554 a related PCI peripheral device, has a 64-bit primary interface, a 64-bit secondary interface, and 33-MHz capability." The 21555 is a "non-transparent" PCI-to-PCI bridge that acts as a gateway to an intelligent subsystem. It allows a local processor to independently configure and control the local subsystem. The 21555 implements an I2O message unit that enables any local processor to function as an intelligent I/O processor (IOP) in an I2O-capable system. Because the 21555 is architecture independent, it works with any host and local processors that support a PCI bus. This architecture independence enables vendors to leverage existing investments while moving products to PCI technology. Unlike a transparent PCI-to-PCI bridge, the 21555 is specifically designed to bridge between two processor domains. The processor domain on the primary interface of the 21555 is also referred to as the host domain, and its processor is the host processor. The secondary bus interfaces to the local domain and the local processor. Special features include support of independent primary and secondary PCI clocks, independent primary and secondary address spaces, and address translation between the primary (host) and secondary (local) domains. The 21555 enables add-in card vendors to present to the host system a higher level of abstraction than is possible with a transparent PCI-to-PCI bridge. The 21555 uses a Type 0 configuration header, which presents the entire subsystem as a single "device" to the host processor. This allows loading of a single device driver for the entire subsystem, and independent local processor initialization and control of the subsystem devices. Because the 21555 uses a Type 0 configuration header, it does not require hierarchical PCI-to-PCI bridge configuration code. The 21555 forwards transactions between the primary and secondary PCI buses as does a transparent PCI-to-PCI bridge. In contrast to a transparent PCI-to-PCI bridge, however, the 21555 can translate the address of a forwarded transaction from a system address to a local address, or vice versa. This mechanism allows the 21555 to hide subsystem resources from the host processor and to resolve any resource conflicts that may exist between the host and local subsystems. The 21555 operates at 3.3 V and is also 5.0-V I/O tolerant. Adapter cards designed using the 21555 can be keyed as universal, thus permitting use in either a 5-V or 3-V slot.
1.1
Comparing 21555 and Standard PCI-to-PCI Bridge
The 21555 is functionally similar to a standard PCI-to-PCI bridge (PPB) in that both provide a connection path between devices attached to two independent PCI buses. A 21555 and a PPB allow the electrical loading of devices on one PCI bus to be isolated from the other bus while permitting concurrent operation on both buses. Because the PCI Local Bus Specification restricts PCI option cards to a single electrical load, the ability of PPBs and the 21555 to spawn PCI buses enables the design of multi device PCI option cards. The key difference between a PPB and the 21555 is that the presence of a PPB in a connection path between the host processor and a device is transparent to devices and device drivers, while the presence of the 21555 is not. This difference enables the 21555 to provide features that better support the use of intelligent controllers in the subsystem.
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Non-Transparent PPB
It was a primary goal of the PCI-to-PCI bridge architecture that a PPB be transparent to devices and device drivers. For example, no changes are needed to a device driver when a PCI peripheral is located behind a PPB. Once configured during system initialization, a PPB operates without the aid of a device driver. A PPB does not require a device driver of its own since it does not have any resources that must be managed by software during run-time. This requirement for transparency forced the usage of a flat addressing model across PCI-to-PCI bridges. This means that a given physical address exists at only one location in the PCI bus hierarchy and that this location may be accessed by any device attached at any point in the PCI bus hierarchy. As a consequence, it is not possible for a PPB to isolate devices or address ranges from access by devices on the opposite interface of a PPB. The PPB architecture assumes that the resources of any device in a PCI system are configured and managed by the host processor. However, there are applications where the transparency of a PCI-to-PCI bridge is not desired. For example, Figure 1 shows a hypothetical PCI add-in card used for an intelligent subsystem application. Figure 1. 21555 Intelligent Controller Application
Intelligent Subsystem
DRAM/ ROM PCI Device PCI Device PCI Device
Memory
Local CPU
CPUPCI Bridge
PCI Bus
Intel(R) 21555 Device
PCI Bus
Host Core Logic
Host CPU
A8826-01
Assume that the local processor on the add-in card is used to manage the resources of the devices attached to the add-in card's local PCI bus. Assume also that it is desirable to restrict access to these same resources from other PCI bus masters in the system and from the host processor. In addition, there is a need to resolve address conflicts that may exist between the host system and the local processor. The non transparency of the 21555 is perfectly suited to this kind of configuration, where a transparent PCI-to-PCI bridge is problematic. Because the 21555 is not transparent, the device driver for the add-in card must be aware of the presence of the 21555 and manage its resources appropriately. The 21555 allows the entire subsystem to appear as a single virtual device to the host. This enables configuration software to identify the appropriate driver for the subsystem. With a transparent PCI-to-PCI bridge, a driver does not need to know about the presence of the bridge and manage its resources. The subsystem appears to the host system as individual PCI devices on a secondary PCI bus, not as a single virtual device. Table 1 shows a comparison between a 21555 and a standard transparent PCI-to-PCI bridge.
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Non-Transparent PPB
Table 1.
21555 and PPB Feature Comparison
Feature 21555 Adheres to PPB ordering rules. Transaction forwarding Uses posted writes and delayed transactions. Adheres to PPB transaction error and parity error guidelines, although some errors may be reported differently. Base address registers are used to define independent downstream and upstream forwarding windows. Address decoding Inverse decoding is only used for upstream transactions above the 4 GB boundary. Address translation Supported for both memory and I/O transactions. Downstream devices are not visible to host. Does not require hierarchical configuration code (Type 0 configuration header). Configuration Does not respond to Type 1 configuration transactions. Supports configuration access from the secondary bus. Implements separate set of configuration registers for the secondary interface. Includes features such as doorbell interrupts, I2O message unit, and so on, that must be managed by the device driver. Generates secondary bus clock output. Clocks Asynchronous secondary clock input is also supported. Implements secondary bus arbiter. This function can be disabled. Secondary bus central functions Drives secondary bus AD, C/BE#, and PAR during reset. This function can be disabled. Inverse decoding for upstream forwarding. No translation, a flat address model is assumed. Downstream devices are visible to host. Requires hierarchical configuration code (Type 1 configuration header). Forwards and converts Type 1 configuration transactions. Does not support configuration access from the secondary bus. Same set of configuration registers is used to control both primary and secondary interfaces. PCI-to-PCI Bridge Adheres to PPB ordering rules. Uses posted writes and delayed transactions. Adheres to PPB transaction error and parity error guidelines. PPB base and limit address registers are used to define downstream forwarding windows.
Run-time resources
Typically has only configuration registers; no device driver is required.
Generates one or more secondary bus clock outputs.
Implements secondary bus arbiter. Drives secondary bus AD, C/BE#, and PAR during reset.
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Non-Transparent PPB
1.2
Architectural Overview
The 21555 consists of the following function blocks: Data Buffers Data buffers include the buffers along with the associated data path control logic. Delayed transaction buffers contain the compare functionality for completing delayed transactions. The blocks also contain the watchdog timers associated with the buffers. The data buffers are as follows:
* * * * * * *
Four-entry downstream delayed transaction buffer Four-entry upstream delayed transaction buffer 256-byte downstream posted write buffer 256-byte upstream posted write buffer 256-byte downstream read data buffer 256-byte upstream read data buffer Two downstream I2O delayed transaction entries
Registers The following register blocks also contain address decode and translation logic, I2O message unit, and interrupt control logic:
* * * *
Primary interface header Type 0 configuration registers Secondary interface header Type 0 configuration registers Device-specific configuration registers Memory and I/O mapped control and status registers
Control Logic The 21555 has the following control logic:
* * * * *
Primary PCI target control logic Primary PCI master control logic Secondary PCI target control logic Secondary PCI master control logic ROM interface control logic for both serial and parallel ROM connections (interfaces between the ROM registers and ROM signals) the 21555 secondary master control logic
* Secondary PCI bus arbiter interface to secondary bus device request and grant lines, as well as * JTAG control logic
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Non-Transparent PPB
Figure 2 shows the 21555 microarchitecture. Figure 2. 21555 Microarchitecture
21555 21555
Downstream Delayed Buffer
Downstream Posted Write Buffer
Upstream Read Data Buffer
Downstream Read Data Buffer
Upstream Posted Write Buffer Secondary PCI Bus
rimary PCI Bus
Upstream Delayed Buffer
Primary Target Control
Primary Config Registers
Primary Master Control
DeviceSpecific Config Registers
CSR Registers
Secondary Config Registers
Secondary Target Control
Secondary Master Control
JTAG
ROM Interface Control
Secondary Bus Arbiter
JTAG Signals
ROM Interface Interrupt Signals Signals
Secondary Arbiter Signals
A7418-01
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2.0
Pin Assignment
This chapter describes the 21555 pin assignment and lists the pins according to location and in alphabetic order. Figure 3 shows the 21555 304-point ball grid array (PBGA), representing the pins in vertical rows labeled numerically, and horizontal rows labeled alphabetically. Table 2 defines the signal type abbreviations used in the signal and pin tables for this specification. Table 3 and Table 4 use these alphanumerics to identify pin assignments.
Table 2.
Signal Type Abbreviations
Signal Type I O TS STS OD Description Standard input only. Standard output only. Tristate bidirectional. Sustained tristate. Active low signal must be pulled high for one clock cycle when deasserting. Standard open drain.
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Figure 3. 21555 PBGA Cavity Down View
Pin 1 Corner
A B C D E F G H J K L M N P R T U V W Y AA AB AC 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A7436-01
21555
Top View (Pin Down)
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Non-Transparent PPB
2.1
Pin Location List (Alphanumeric)
Table 3 lists the 21555 pins in order of location, showing the location code, signal name, and signal type of each pin. Figure 3 provides the map for identifying the pin location codes, listed in alphanumeric order in the PBGA Location column. Table 2 defines the signal type abbreviations used in the Type column.
Table 3.
21555 Pin Location List (Alphanumeric) (Sheet 1 of 5)
PBGA Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AA1 AA2 AA3 AA4 AA5 AA6 Signal Name s_req_l[4] s_req_l[3] s_req_l[1] s_ad[29] s_ad[27] s_ad[25] s_cbe_l[3] s_ad[22] s_ad[20] s_ad[16] s_frame_l s_devsel_l s_par s_ad[13] s_ad[10] s_m66ena s_cbe_l[0] s_ad[6] s_ad[3] s_ad[1] s_req64_l vdd s_cbe_l[6] p_ad[18] vss p_ad[17] vss vdd p_par Type I I I TS TS TS TS TS TS TS STS STS TS TS TS I TS TS TS TS STS P TS TS P TS P P TS PBGA Location AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 Signal Name p_ad[12] p_ad[10] p_cbe_l[0] p_ad[5] vss vdd vss p_cbe_l[7] p_cbe_l[4] vdd p_ad[58] p_ad[54] vss vdd p_ad[46] p_ad[42] vdd p_ad[16] vss p_trdy_l p_stop_l p_serr_l p_ad[15] vss vss p_ad[8] p_ad[6] vdd p_ad[1] Type TS TS TS TS P P P TS TS P TS TS P P TS TS P TS P STS STS OD TS P P TS TS P TS
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Table 3.
21555 Pin Location List (Alphanumeric) (Sheet 2 of 5)
PBGA Location AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 B1 B2 B3 Signal Name p_ad[0] p_cbe_l[6] p_ad[63] p_ad[60] vss p_ad[55] p_ad[53] p_ad[51] p_ad[48] vss vdd vdd vdd p_frame_l p_devsel_l p_perr_l p_cbe_l[1] p_ad[14] p_ad[11] p_m66ena p_ad[7] p_ad[3] p_ad[2] p_ack64_l p_cbe_l[5] p_ad[61] p_ad[59] p_ad[56] vdd p_ad[52] p_ad[50] p_ad[47] p_ad[45] p_ad[44] vdd vss s_req_l[0] Type TS TS TS TS P TS TS TS TS P P P P STS STS STS TS TS TS I TS TS TS STS TS TS TS TS P TS TS TS TS TS P P I PBGA Location B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Signal Name vdd s_ad[26] s_ad[24] s_idsel vss s_ad[18] vss vss s_trdy_l s_serr_l s_ad[14] s_ad[12] vdd s_ad[9] s_ad[7] s_ad[4] vdd vss vss vdd s_req_l[6] s_req_l[7] s_req_l[2] s_ad[31] s_ad[28] vss s_ad[23] s_ad[21] s_ad[17] vdd s_irdy_l s_stop_l s_perr_l s_ad[15] vdd vss vss Type P TS TS I P TS P P STS OD TS TS P TS TS TS P P P P I I I TS TS P TS TS TS P STS STS STS TS P P P
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Table 3.
21555 Pin Location List (Alphanumeric) (Sheet 3 of 5)
PBGA Location C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 Signal Name s_ad[5] s_ad[2] s_ack64_l s_cbe_l[5] s_par64 s_cbe_l[4] s_gnt_l[1] s_gnt_l[2] s_req_l[8] s_req_l[5] s_ad[30] vdd vdd vss s_ad[19] vdd s_cbe_l[2] vss s_cbe_l[1] vdd s_ad[11] vss s_ad[8] vdd s_ad[0] s_cbe_l[7] vss s_ad[61] s_ad[62] s_rst_in_l s_gnt_l[4] s_gnt_l[3] s_gnt_l[0] s_ad[63] s_ad[60] s_ad[58] s_ad[59] Type TS TS STS TS TS TS TS TS I I TS P P P TS P TS P TS P TS P TS P TS TS P TS TS I TS TS TS TS TS TS TS PBGA Location F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G20 G21 G22 G23 H1 H2 H3 H4 H20 H21 H22 H23 J1 J2 J3 J4 J20 J21 J22 J23 K1 K2 K3 K4 K20 Signal Name s_gnt_l[6] s_gnt_l[7] s_gnt_l[5] vss vss vss s_ad[56] s_ad[57] s_gnt_l[8] vss s_clk s_clk_o vdd s_ad[53] s_ad[54] s_ad[55] s_rst_l s_inta_l tdi vdd vdd s_ad[50] s_ad[51] s_ad[52] tdo tck trst_l tms vdd s_ad[47] s_ad[48] s_ad[49] sr_cs pr_ad[7] pr_ad[6] vss vss Type TS TS TS P P P TS TS TS P I O P TS TS TS O OD I P P TS TS TS O I I I P TS TS TS O TS TS P P
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Table 3.
21555 Pin Location List (Alphanumeric) (Sheet 4 of 5)
PBGA Location k21 k22 k23 L1 L2 L3 L4 L20 L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 Signal Name s_ad[45] vss s_ad[46] pr_ad[4] pr_ad[3] pr_ad[2] pr_ad[5] s_ad[44] s_ad[42] s_ad[41] s_ad[43] pr_ad[0] pr_rd_l pr_ad[1] vdd vdd vdd s_ad[40] vss pr_wr_l pr_ale_l pr_cs_l / pr_rdy pr_clk s_ad[36] s_ad[39] s_ad[38] s_ad[37] p_rst_l p_inta_l scan_ena vss vss s_ad[35] s_ad[34] vss p_gnt_l vss Type TS P TS TS TS TS TS TS TS TS TS TS O TS P P P TS P O O O/I O TS TS TS TS I OD I P P TS TS P I P PBGA Location R3 R4 R20 R21 R22 R23 T1 T2 T3 T4 T20 T21 T22 T23 U1 U2 U3 U4 U20 U21 U22 u23 V1 V2 V3 V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22 Signal Name vdd p_clk l_stat s_ad[33] s_ad[32] s_pme_l p_ad[30] p_ad[31] p_req_l vdd vdd s_vio p_enum_l p_pme_l p_ad[27] p_ad[29] vss p_ad[28] p_par64 p_vio vdd p_ad[32] p_ad[25] p_ad[26] p_ad[24] vss vss p_ad[35] p_ad[33] p_ad[34] p_idsel p_cbe_l[3] p_ad[23] p_ad[20] p_ad[40] p_ad[38] p_ad[36] Type P I TS TS TS I TS TS TS P P I OD OD TS TS P TS TS I P TS TS TS TS P P TS TS TS I TS TS TS TS TS TS
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Table 3.
21555 Pin Location List (Alphanumeric) (Sheet 5 of 5)
PBGA Location W23 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 Signal Name p_ad[37] p_ad[21] p_ad[22] p_ad[19] p_cbe_l[2] p_irdy_l vdd p_ad[13] vss p_ad[9] vdd p_ad[4] Type TS TS TS TS TS STS P TS P TS P TS PBGA Location y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 Signal Name vss p_req64_l vdd p_ad[62] vss p_ad[57] vdd p_ad[49] p_ad[43] p_ad[41] p_ad[39] vss Type P STS P TS P TS P TS TS TS TS P
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2.2
Pin Signal List (Alphanumeric)
Table 4 lists the 21555 signals in alphanumeric order, showing the name, location code, and type of each signal. Figure 3 provides the map for identifying the pin location codes that are listed under PBGA Location column. Table 2 defines the signal type abbreviations used in the Type column.
Table 4.
21555 Pin Signal List (Alphanumeric) (Sheet 1 of 5)
Signal Name l_stat p_ack64_l p_ad[0] p_ad[1] p_ad[2] p_ad[3] p_ad[4] p_ad[5] p_ad[6] p_ad[7] p_ad[8] p_ad[9] p_ad[10] p_ad[11] p_ad[12] p_ad[13] p_ad[14] p_ad[15] p_ad[16] p_ad[17] p_ad[18] p_ad[19] p_ad[20] p_ad[21] p_ad[22] p_ad[23] p_ad[24] p_ad[25] p_ad[26] PBGA Location R20 AC13 AB13 AB12 AC12 AC11 Y11 AA10 AB10 AC10 AB9 Y9 AA8 AC8 AA7 Y7 AC7 AB6 AB1 AA3 AA1 Y3 W4 Y1 Y2 W3 V3 V1 V2 Type TS STS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS Signal Name p_ad[27] p_ad[28] p_ad[29] p_ad[30] p_ad[31] p_ad[32] p_ad[33] p_ad[34] p_ad[35] p_ad[36] p_ad[37] p_ad[38] p_ad[39] p_ad[40] p_ad[41] p_ad[42] p_ad[43] p_ad[44] p_ad[45] p_ad[46] p_ad[47] p_ad[48] p_ad[49] p_ad[50] p_ad[51] p_ad[52] p_ad[53] p_ad[54] p_ad[55] PBGA Location U1 U4 U2 T1 T2 U23 V22 V23 V21 W22 W23 W21 Y22 W20 Y21 AA22 Y20 AC23 AC22 AA21 AC21 AB21 Y19 AC20 AB20 AC19 AB19 AA18 AB18 Type TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS
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Table 4.
21555 Pin Signal List (Alphanumeric) (Sheet 2 of 5)
Signal Name p_ad[56] p_ad[57] p_ad[58] p_ad[59] p_ad[60] p_ad[61] p_ad[62] p_ad[63] p_cbe_l[0] p_cbe_l[1] p_cbe_l[2] p_cbe_l[3] p_cbe_l[4] p_cbe_l[5] p_cbe_l[6] p_cbe_l[7] p_clk p_devsel_l p_enum_l p_frame_l p_gnt_l p_idsel p_inta_l p_irdy_l p_m66ena p_par p_par64 p_perr_l p_pme_l p_req_l p_req64_l p_rst_l p_serr_l p_stop_l p_trdy_l pr_ad[0] pr_ad[1] PBGA Location AC17 Y17 AA17 AC16 AB16 AC15 Y15 AB15 AA9 AC6 Y4 W2 AA15 AC14 AB14 AA14 R4 AC4 T22 AC3 R1 W1 P2 Y5 AC9 AA6 U20 AC5 T23 T3 Y13 P1 AB5 AB4 AB3 M1 M3 Type TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS I STS OD STS I I OD STS I TS TS STS OD TS STS I OD STS STS TS TS Signal Name pr_ad[2] pr_ad[3] pr_ad[4] pr_ad[5] pr_ad[6] pr_ad[7] pr_ale_l pr_clk pr_cs_l / pr_rdy pr_rd_l pr_wr_l p_vio s_ack64_l s_ad[0] s_ad[1] s_ad[2] s_ad[3] s_ad[4] s_ad[5] s_ad[6] s_ad[7] s_ad[8] s_ad[9] s_ad[10] s_ad[11] s_ad[12] s_ad[13] s_ad[14] s_ad[15] s_ad[16] s_ad[17] s_ad[18] s_ad[19] s_ad[20] s_ad[21] s_ad[22] s_ad[23] PBGA Location L3 L2 L1 L4 K3 K2 N2 N4 N3 M2 N1 U21 C20 D19 A20 C19 A19 B19 C18 A18 B18 D17 B17 A15 D15 B15 A14 B14 C14 A10 C9 B9 D9 A9 C8 A8 C7 Type TS TS TS TS TS TS O O O/I O O I STS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS
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Table 4.
21555 Pin Signal List (Alphanumeric) (Sheet 3 of 5)
Signal Name s_ad[24] s_ad[25] s_ad[26] s_ad[27] s_ad[28] s_ad[29] s_ad[30] s_ad[31] s_ad[32] s_ad[33] s_ad[34] s_ad[35] s_ad[36] s_ad[37] s_ad[38] s_ad[39] s_ad[40] s_ad[41] s_ad[42] s_ad[43] s_ad[44] s_ad[45] s_ad[46] s_ad[47] s_ad[48] s_ad[49] s_ad[50] s_ad[51] s_ad[52] s_ad[53] s_ad[54] s_ad[55] s_ad[56] s_ad[57] s_ad[58] s_ad[59] s_ad[60] PBGA Location B6 A6 B5 A5 C5 A4 D5 C4 R22 R21 P22 P21 N20 N23 N22 N21 M22 L22 L21 L23 L20 K21 K23 J21 J22 J23 H21 H22 H23 G21 G22 G23 F22 F23 E22 E23 E21 Type TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS Signal Name s_ad[61] s_ad[62] s_ad[63] s_cbe_l[0] s_cbe_l[1] s_cbe_l[2] s_cbe_l[3] s_cbe_l[4] s_cbe_l[5] s_cbe_l[6] s_cbe_l[7] s_clk s_clk_o s_devsel_l s_frame_l s_gnt_l[0] s_gnt_l[1] s_gnt_l[2] s_gnt_l[3] s_gnt_l[4] s_gnt_l[5] s_gnt_l[6] s_gnt_l[7] s_gnt_l[8] s_idsel s_inta_l s_irdy_l s_m66ena s_par s_par64 s_perr_l s_pme_l s_req_l[0] s_req_l[1] s_req_l[2] s_req_l[3] s_req_l[4] PBGA Location D22 D23 E20 A17 D13 D11 A7 C23 C21 A23 D20 G3 G4 A12 A11 E4 D1 D2 E3 E2 F3 F1 F2 G1 B7 H2 C11 A16 A13 C22 C13 R23 B3 A3 C3 A2 A1 Type TS TS TS TS TS TS TS TS TS TS TS I O STS STS TS TS TS TS TS TS TS TS TS I OD STS I TS TS STS I I I I I I
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Table 4.
21555 Pin Signal List (Alphanumeric) (Sheet 4 of 5)
Signal Name s_req_l[5] s_req_l[6] s_req_l[7] s_req_l[8] s_req64_l s_rst_in_l s_rst_l s_serr_l s_stop_l s_trdy_l scan_ena sr_cs s_vio tck tdi tdo tms trst_l vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd PBGA Location D4 C1 C2 D3 A21 E1 H1 B13 C12 B12 P3 K1 T21 J2 H3 J1 J4 J3 A22 AA5 AA12 AA16 AA20 AA23 AB11 AB23 AC1 AC2 AC18 B1 B4 B16 B20 B23 C10 C15 D6 Type I I I I STS I O OD STS STS I O I I I O I I P P P P P P P P P P P P P P P P P P P Signal Name vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss PBGA Location D7 D10 D14 D18 G20 H4 H20 J20 M4 M20 M21 R3 T4 T20 U22 Y6 Y10 Y14 Y18 AA2 AA4 AA11 AA13 AA19 AB2 AB7 AB8 AB17 AB22 B2 B8 B10 B11 B21 B22 C6 C16 Type P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
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Table 4.
21555 Pin Signal List (Alphanumeric) (Sheet 5 of 5)
Signal Name vss vss vss vss vss vss vss vss vss vss vss vss PBGA Location C17 D8 D12 D16 D21 F4 F20 F21 G2 K4 K20 K22 Type P P P P P P P P P P P P Signal Name vss vss vss vss vss vss vss vss vss vss vss vss PBGA Location M23 P4 P20 P23 R2 U3 V4 V20 Y8 Y12 Y16 Y23 Type P P P P P P P P P P P P
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3.0
Electrical Specifications
This section specifies the following electrical behavior of the 21555:
* * * *
PCI electrical conformance. Absolute maximum ratings. DC specifications. AC timing specifications.
3.1
PCI Electrical Specification Conformance
The 21555 PCI pins conform to the basic set of PCI electrical specifications in the PCI Local Bus Specification, Revision 2.2. See that document for a complete description of the PCI I/O protocol and pin AC specifications.
3.2
Absolute Maximum Ratings
The 21555 is specified to operate at a maximum frequency of 33 MHz or 66 MHz if 66 MHz capable, at a junction temperature (Tj) not to exceed 125C. Table 5 lists the absolute maximum ratings for the 21555. Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress ratings only. Operating beyond the functional operating range is not recommended and extended exposure beyond the functional operating range may affect reliability. Table 6 lists the functional operating range.
Table 5.
Absolute Maximum Ratings
Parameter Junction temperature, Tj Supply voltage Vcc Maximum voltage applied to signal pins Maximum power, PWC Storage temperature range, Tstg Minimum -- -- -- -- -55C Maximum 125C 4.3 V 5.5 V 3.0 W 125C
.
Table 6.
Functional Operating Range
Parameter Supply voltage, Vcc Operating ambient temperature, Ta Minimum 3.0 V 0C Maximum 3.6 V 70C
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3.3
DC Specifications
Table 7 defines the DC parameters met by all 21555 signals under the conditions of the functional operating range. Note: In Table 7, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from the chip (chip sourcing) are denoted as negative (-) current. DC Parameters
Symbol Vcc Vil Vih Vol Vol5V Voh Voh5V Iil Cin CIDSEL Cclk
a. b. c. d.
Table 7.
Parameter Supply voltage Low-level input voltage
a
Condition -- -- -- Iout = 1500 A Iout = 6 mA Iout = -500 A Iout = -2 mA
a,d
Minimum 3.0 -0.5 0.5 Vcc -- -- 0.9 Vcc 2.4 -- -- -- 5.0
Maximum 3.6 0.3 Vcc VIO + 0.5 V 0.1 Vcc 0.55 -- -- 10 10.0 8.0 12.0
Unit V V V V V V V A pF pF pF
High-level input voltagea Low-level output voltage Low-level output voltage
b c b
High-level output voltage
High-level output voltagec Low-level input leakage current Input pin capacitance p_idsel pin capacitance p_clk, s_clk pin capacitance
0 Guarantees meeting the specification for the 5-V signaling environment. For 3.3-V signaling environment. For 5-V signaling environment. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
3.4
AC Timing Specifications
The next sections specify the AC characteristics met by all 21555 signals under the conditions of the functional operating range:
* * * * * * 3.4.1
Clock timing. PCI signal timing. Reset timing. Serial ROM timing. Parallel ROM timing. JTAG timing.
Clock Timing Specifications
The AC specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. The output responses are delays from clock to signal. The AC specifications are defined separately for each clock domain within the 21555.
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Table 8 and Table 9 specify p_clk and s_clk parameter values for clock signal AC timing, and Figure 4 shows the AC parameter measurements for the p_clk and s_clk signals. See also Figure 5 for a further illustration of signal timing. Unless otherwise indicated, all AC parameters are guaranteed when tested within the functional operating range of Table 6. Table 8. 33 MHz PCI Clock Signal AC Parameters
Symbol Tcyc Thigh Tlow - Tsclk Tsclkr Tsclkf Tdskew Parameter p_clk,s_clk cycle time p_clk, s_clk high time p_clk, s_clk low time p_clk, s_clk slew rate
a
Minimum 30 11 11 1 3 0
c C
Maximum
Unit ns ns ns V/ns ns ns ns ns
-- -- 4 15 8 8 0.75
Delay from p_clk to s_clkb p_clk rising to s_clk_o rising p_clk falling to s_clk_o falling
0 --
s_clk_o duty cycle skew from p_clk duty cycle
a. 0.2 VCC to 0.6 VCC. b. Required when the 21555 is operating in synchronous mode. c. Measured with 30 pF lumped load.
Table 9.
66 MHz PCI Clock Signal AC Parameters
Symbol Tcyc Thigh Tlow - Tsclk Tsclkr Tsclkf Tdskew Parameter p_clk,s_clk cycle time p_clk, s_clk high time p_clk, s_clk low time p_clk, s_clk slew rate
a b
Minimum 15 6 6 1.5 3 0 0
C
Maximum 30 -- -- 4 15 13 13 0.75
Unit ns ns ns V/ns ns ns ns ns
Delay from p_clk to s_clk
p_clk rising to s_clk_o rising p_clk falling to s_clk_o fallingc s_clk_o duty cycle skew from p_clk duty cycle
--
a. 0.2 VCC to 0.6 VCC. b. Required when the 21555 is operating in synchronous mode. c. Measured with 30 pF lumped load.
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Figure 4. PCI Clock Signal AC Parameter Measurements
Tcyc Vt1 Vt2 Vt3 Tr
Tr Vt1 Vt2 Thigh
Thigh Tlow Tf
Tf Tlow
p_clk
s_clk
Vt3 Tskew Tskew
Tcyc Notes: Tt1 - 2.0 V for 5-V signals; 0.5 Vcc for 3.3-V clocks Tt2 - 1.5 V for 5-V signals; 0.4 Vcc for 3.3-V clocks Tt3 - 0.8 V for 5-V signals; 0.3 Vcc for 3.3-V clocks
A7834-01
3.4.2
PCI Signal Timing Specifications
Figure 5 and Tables 10 and 11 show the PCI signal timing specifications.
Figure 5. PCI Signal Timing Measurement Conditions
CLK
Vtest Tval Tinval Valid Ton Toff Valid Tsu Th
Output
Input
Note: Ttest - 1.5 V for 5-V signals; 0.4 Vcc for 3.3-V signals
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Table 10. 33 MHz PCI Signal Timing Specifications
Symbol Tval Tval(ptp) Ton Toff Tsu Tsu(ptp) Th Parameter CLK to signal valid delay -- bused signals CLK to signal valid delay -- point-to-point Float to active delaya,b Active to float delay
a,b a,b,c a,b,c
Minimum 2 2 2 -- 7 10, 12 0
Maximum 11 12 -- 28 -- -- --
Unit ns ns ns ns ns ns ns
a,b,c
Input setup time to CLK -- bused signals Input setup time to CLK--point-to-point Input signal hold time from CLKa,b
a,b,c
a. See Figure 5. b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk. c. Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par, s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
Table 11. 66 MHz PCI Signal Timing Specifications
Symbol Tval Tval(ptp) Ton Toff Tsu Tsu(ptp) Th Parameter CLK to signal valid delay -- bused signalsa,b,c CLK to signal valid delay -- point-to-point Float to active delay Active to float delay
a,b a,b,c
Minimum 2 2 2 -- 3 5 0
Maximum 6 6 -- 14 -- -- --
Unit ns ns ns ns ns ns ns
a,b
Input setup time to CLK -- bused signalsa,b Input setup time to CLK--point-to-pointa,b Input signal hold time from CLK
a,b
a. See Figure 5. b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk. c. Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64, p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par, s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
3.4.3
Reset Timing Specifications
Table 12 shows the reset timing specifications for p_rst_l and s_rst_l.
Table 12. Reset Timing Specifications (Sheet 1 of 2)
Symbol Trst Trst-clk Trst-off Tsrst Tsrst-on Tdsrst - Parameter p_rst_l active time after power stable p_rst_l active time after p_clk stable p_rst_l active-to-output float delay s_rst_l active after p_rst_l assertion s_rst_l active time after s_clk stable s_rst_l deassertion after p_rst_l deassertion p_rst_l slew rate
a
Minimum 1 100 -- -- 100 0 50
Maximum -- -- 40 40 -- 25 --
Unit s s ns ns s Cycles mV/ns
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Table 12. Reset Timing Specifications (Sheet 2 of 2)
Symbol Trrsus Trrval Trrsu Trrh Parameter s_req64_l asserted to s_rst_l deasserted s_rst_l to s_req64_l deasserted delay time REQ64# to RST# deasserting setup time REQ64# from RST# deasserting hold time Minimum 10*Tcyc 0 Tcyc Tcyc 0 Maximum -- -- -- 50 Unit nsa nsa ns ns
a. Applies to rising (deasserting) edge only.
3.4.4
Serial ROM Timing Specifications
Table 13 shows the serial ROM timing specifications.
Table 13. Serial ROM Timing Specifications
Symbol Tscval Tson Tsoff Tssu Tsh Tsmcs Tscyc Parameter pclk to pr_ad[0] serial ROM clock valid pr_ad float to active delay pr_ad active to float delay pr_ad[1] di to pr_ad[0] serial ROM clock setup time pr_ad[1] to pr_ad[0] serial ROM clock hold time sr_cs minimum low time pr_ad[0] serial ROM clock cycle time Minimum -- 2 -- 400 20 400 1000 Maximum 14 -- 28 -- -- -- -- Unit ns ns ns ns ns ns ns
3.4.5
Parallel ROM Timing Specifications
Table 14 shows the parallel ROM timing specifications.
Table 14. Parallel ROM Timing Specifications
Symbol Tpas Tpcc Tpacs Tpcsl Tpcrw Tprs Tprh Tprv Parameter pr_ale_l setup to pr_clk rising pr_clk cycle time pr_ale_l rising to pr_cs_l falling pr_cs_l low pr_cs_l falling to pr_rd_l or pr_wr_l falling pr_ad setup time to pr_rd_l rising pr_ad hold time from pr_rd_l rising pr_clk rising to pr_ad valid Minimum 30 60 25 200 25 180 0 0 Maximum -- -- -- -- -- -- -- 15 Unit ns ns ns ns ns ns ns ns
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3.4.6
JTAG Timing Specifications
Table 15 shows the JTAG timing specifications.
Table 15. JTAG Timing Specifications
Symbol Tjr Tjp Tght Tglt Tjrt Tgft Tjs Tjh Tjd Tjfd Parameter tck frequency tck period tck high time tck low time tck rise time tck fall time
a
Minimum 0 200 100 100 -- -- 10 25 -- --
Maximum 5
Unit MHz ns ns ns ns ns ns ns ns ns
-- -- 10 10 -- -- 30 30
b
tdi, tms setup time to tck rising edge tdi, tms hold time from tck rising edge tdo valid delay from tck falling edge tdo float delay from tck falling edge
c
a. Measured between 0.8 V and 2.0 V. b. Measured between 2.0 V and 0.8 V. c. C1=50 pF.
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4.0
Mechanical Specifications
The 21555 is contained in an industry-standard 304 PBGA, a four-layer plastic ball grid array package, as shown in Figure 6.
Figure 6. 304 PBGA (Four-Layer) Package
_ D A _
aaa
_C_
Pin 1 Corner Pin 1 I.D.
D1 _B_
// bbb C
30o
E1
E
Top View
A2 A1 A
22 20 18 16 14 12 10 08 06 04 02 23 21 19 17 15 13 11 09 07 05 03 01 A B C D E F G H J K L M N P R T U V W Y AA AB AC e
Pin 1 Corner b/ / 0.30
S
C
CAS B
S
21555
e
(J)
Notes:
Bottom View
(I)
(
_ Basic Dimension ) _ Reference Dimension
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Table 16 lists the package dimensions in millimeters. Table 16. 304-Point 4-Layer PBGA Package Dimensions
Symbol e A A1 A2 b C aaa bbb D D1 E E1 I J Dimension Ball pitch Overall package height Package standoff height Encapsulation thickness Ball diameter Substrate thickness Coplanarity Overall package planarity Overall package width Overall encapsulation width Overall package width Overall encapsulation width Location of first row (x-direction) Location of first row (y-direction) -- -- 30.80 -- 30.80 -- -- -- Minimum Value -- 2.12 0.50 1.12 0.60 Nominal Value 1.27 BSCa 2.33 0.60 1.17 0.76 0.56 referenceb -- -- 31.00 26.00 31.00 26.00 1.53 referenceb 1.53 reference
b
Maximum Value -- 2.54 0.70 1.22 0.90
0.2 0.15 31.20 26.70 31.20 26.70 -- --
a. ANSI Y14.5M-1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension (BSC) as: A numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or datum target. It is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in feature control frames. b. The value for this measurement is for reference only.
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